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d a t a sh eet product speci?cation supersedes data of 2003 sept 30 2004 may 19 tda8754 triple 8-bit video adc up to 270 msps integrated circuits
2004 may 18 2 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 7.1 lqfp144 package 7.2 lbga208 package 8 functional description 8.1 power management 8.1.1 standby mode 8.1.2 power-down mode 8.2 analog video input 8.2.1 analog multiplexers 8.2.2 activity detection 8.2.3 adc 8.2.4 clamp 8.2.5 agc 8.3 hsosel, deo and schckrefo 8.4 pll 8.5 sync-on-green 8.6 programmable coast 8.7 data enable 8.8 sync separator 8.9 3-level 9i 2 c-bus register description 9.1 i 2 c-bus formats 9.1.1 write 1 register 9.1.2 write all registers 9.1.3 read register 9.2 i 2 c-bus registers overview 9.3 offset registers (r, g and b) 9.4 coarse registers (r, g and b) 9.5 fine registers (r, g and b) 9.6 sog register 9.7 pll control 9.8 phase register 9.9 pll divider registers 9.10 horizontal sync registers 9.11 coast register 9.12 horizontal sync selection register 9.13 vertical sync selection register 9.14 clamp register 9.15 inverter register 9.16 output register 9.17 output enable register 1 9.18 output enable register 2 9.19 clock output register 9.20 internal oscillator register 9.21 power management register 9.22 read register 9.23 version register 9.24 sign detection register 9.25 activity detection register 1 9.26 activity detection register 2 10 limiting values 11 thermal characteristics 12 characteristics 13 timing 14 application information 15 package outlines 16 soldering 16.1 introduction to soldering surface mount packages 16.2 reflow soldering 16.3 wave soldering 16.4 manual soldering 16.5 suitability of surface mount ic packages for wave and reflow soldering methods 17 data sheet status 18 definitions 19 disclaimers 20 purchase of philips i 2 c components
2004 may 18 3 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 1 features 3.3 v power supply triple 8-bit adc: C 0.25 lsb differential non-linearity (dnl) C 0.6 lsb integral non-linearity (inl). analog sampling rate from 12 msps up to 270 msps maximum data rate: C single port mode: 140 mhz C dual port mode: 270 mhz C 3.3 v lv-ttl outputs. pll control via i 2 c-bus: C 390 ps pll jitter peak to peak at 270 mhz C low pll drift with temperature (2 phase steps maximum) C pll generates the adc sampling clock which can be locked on the line frequency from 15 khz to 150 khz C integrated pll divider C programmable phase clock adjustment cells. three clamp circuits for programming a clamp code from - 24 to +136 by steps of 1 lsb (mid-scale clamping for yuv signal) internal generation of clamp signal three independent blanking functions input: C 700 mhz analog bandwidth C two independent analog inputs selectable via i 2 c-bus C analog input from 0.5 v to 1 v (p-p) to produce a full-scale adc input of 1 v (p-p) C three controllable amplifiers: gain control via i 2 c-bus to produce full-scale peak-to-peak output with a half lsb resolution. synchronisation: C frame and field detection for interlaced video signal C parasite synchronization pulse detection and suppression C sync processing for composite sync, 3-level sync and sync-on-green signals C polarity and activity detection. ic control via i 2 c-bus serial interface power-down mode lqfp144 and lbga208 package: C lbga208 package pin to pin compatible with tda8756. 2 applications rgb/yuv high-speed digitizing lcd panels drive lcd projection system new tv concept. 3 general description the tda8754 is a complete triple 8-bit adc with an integrated pll running up to 270 msps and analog preprocessing functions (clamp and pga) optimized for capturing rgb/yuv graphic signals. the pll generates a pixel clock from inputs hsync and coast. the tda8754 offers full sync processing for sync-on-green applications. a clamp signal may be generated internally or provided externally. the clamp levels, gains and other settings are controlled via the i 2 c-bus interface. this ic supports display resolutions up to qxga (2048 1536) at 85 hz.
2004 may 18 4 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 4 quick reference data 5 ordering information note 1. values are not yet guaranteed. symbol parameter conditions min. typ. max. unit v cca analog supply voltage 3.0 3.3 3.6 v v ccd digital supply voltage 3.0 3.3 3.6 v v cco output supply voltage 3.0 3.3 3.6 v f pll analog pll frequency 12 - 270 mhz enob effective number of bits f clk = 270 mhz; f i =10mhz - 7.6 - bits inl integral non-linearity f clk = 270 mhz; f i =10mhz - 0.6 1.3 lsb dnl differential non-linearity f clk = 270 mhz; f i =10mhz - 0.25 0.6 lsb p tot power dissipation - 1 1.3 w type number package sampling frequency name description version tda8754hl/11 lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 110 mhz tda8754hl/14 140 mhz tda8754hl/17 170 mhz tda8754hl/21 210 mhz tda8754hl/27 270 mhz tda8754el/11 lbga208 (1) plastic low pro?le ball grid array package; 208 balls; body 17 17 1.05 mm sot774-1 110 mhz tda8754el/14 140 mhz tda8754el/17 170 mhz tda8754el/21 210 mhz tda8754el/27 270 mhz
2004 may 18 5 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 6 block diagram handbook, full pagewidth mgu895 tda8754 pll clkdmx activity detection 3 3 3 clamp agc adc dmx i 2 c-bus slave lv-ttl buffers lv-ttl buffers power management hcounter sync separator deo vsync1 coast vsync2 hsync2 chsync2 hsync1 chsync1 sogin1 sogin2 rgb1 input rgb2 input ckdata hpdo rgb output a rgb output b hsynco vsynco scl a0 sda fieldo ckext ckrefo fig.1 block diagram.
2004 may 18 6 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 7 pinning 7.1 lqfp144 package symbol pin description gndd(ttl) 1 ttl input digital ground v ccd(ttl) 2 ttl input digital supply voltage hsync2 3 horizontal synchronization pulse input 2 chsync2 4 composite horizontal synchronization pulse input 2 v cca(pll) 5 pll analog supply voltage hsync1 6 horizontal synchronization pulse input 1 chsync1 7 composite horizontal synchronization pulse input 1 gnda(pll) 8 pll analog ground cz 9 pll ?lter input gnda(cpo) 10 cpo analog ground cp 11 pll ?lter input pmo 12 phase measurement output (test) gnda(sub) 13 sub analog ground capsogin1 14 decoupling sog input 1 capsogo 15 decoupling sog output capsogin2 16 decoupling sog input 2 gnda(sog) 17 sog analog ground sogin1 18 sync-on-green input 1 v cca(sog) 19 sog analog supply voltage sogin2 20 sync-on-green input 2 v cca(r) 21 red channel analog supply voltage rin1 22 red channel analog input 1 gnda(r1) 23 red channel 1 analog ground rin2 24 red channel analog input 2 gnda(r2) 25 red channel 2 analog ground dec 26 main regulator decoupling input rbot 27 red channel ladder decoupling input rclpc 28 red channel clamp capacitor input v cca(g) 29 green channel analog supply voltage gin1 30 green channel analog input 1 gnda(g1) 31 green channel 1 analog ground gin2 32 green channel analog input 2 gnda(g2) 33 green channel 2 analog ground gbot 34 green channel ladder decoupling input gclpc 35 green channel clamp capacitor input v cca(b) 36 blue channel analog supply voltage bin1 37 blue channel analog input 1 gnda(b1) 38 blue channel 1 analog ground
2004 may 18 7 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 bin2 39 blue channel analog input 2 gnda(b2) 40 blue channel 2 analog ground bbot 41 blue channel ladder decoupling input bclpc 42 blue channel clamp capacitor input agco 43 agc output gndd(adc) 44 adc digital ground v ccd(adc) 45 adc digital supply voltage gndd(sub) 46 sub digital ground pwd 47 power-down control input test 48 test input; must be connected to ground bb0 49 blue channel adc output b bit 0 bb1 50 blue channel adc output b bit 1 bb2 51 blue channel adc output b bit 2 bb3 52 blue channel adc output b bit 3 bb4 53 blue channel adc output b bit 4 bb5 54 blue channel adc output b bit 5 bb6 55 blue channel adc output b bit 6 bb7 56 blue channel adc output b bit 7 v cco(bb) 57 blue channel b output supply voltage gndo(bb) 58 blue channel b output ground bor 59 blue channel adc output bit out of range ba0 60 blue channel adc output a bit 0 ba1 61 blue channel adc output a bit 1 ba2 62 blue channel adc output a bit 2 ba3 63 blue channel adc output a bit 3 ba4 64 blue channel adc output a bit 4 ba5 65 blue channel adc output a bit 5 ba6 66 blue channel adc output a bit 6 ba7 67 blue channel adc output a bit 7 v cco(ba) 68 blue channel a output supply voltage gndo(ba) 69 blue channel a output ground gb0 70 green channel adc output b bit 0 gb1 71 green channel adc output b bit 1 gb2 72 green channel adc output b bit 2 gb3 73 green channel adc output b bit 3 gb4 74 green channel adc output b bit 4 gb5 75 green channel adc output b bit 5 gb6 76 green channel adc output b bit 6 gb7 77 green channel adc output b bit 7 v cco(gb) 78 green channel b output supply voltage gndo(gb) 79 green channel b output ground symbol pin description
2004 may 18 8 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 gor 80 green channel adc output bit out of range ga0 81 green channel adc output a bit 0 ga1 82 green channel adc output a bit 1 ga2 83 green channel adc output a bit 2 ga3 84 green channel adc output a bit 3 ga4 85 green channel adc output a bit 4 ga5 86 green channel adc output a bit 5 ga6 87 green channel adc output a bit 6 ga7 88 green channel adc output a bit 7 v cco(ga) 89 green channel a output supply voltage gndo(ga) 90 green channel a output ground rb0 91 red channel adc output b bit 0 rb1 92 red channel adc output b bit 1 rb2 93 red channel adc output b bit 2 rb3 94 red channel adc output b bit 3 rb4 95 red channel adc output b bit 4 rb5 96 red channel adc output b bit 5 rb6 97 red channel adc output b bit 6 rb7 98 red channel adc output b bit 7 v cco(rb) 99 red channel b output supply voltage gndo(rb) 100 red channel b output ground ror 101 red channel adc output bit out of range ra0 102 red channel adc output a bit 0 ra1 103 red channel adc output a bit 1 ra2 104 red channel adc output a bit 2 ra3 105 red channel adc output a bit 3 ra4 106 red channel adc output a bit 4 ra5 107 red channel adc output a bit 5 ra6 108 red channel adc output a bit 6 ra7 109 red channel adc output a bit 7 v cco(ra) 110 red channel a output supply voltage gndo(ra) 111 red channel a output ground v cco(clk) 112 clock output digital supply voltage ckdata 113 data clock output gndo(clk) 114 clock output digital ground gndd(i2c) 115 i 2 c-bus lines digital ground v ccd(i2c) 116 i 2 c-bus lines digital supply voltage a0 117 i 2 c-bus address control input sda 118 i 2 c-bus serial data input and output scl 119 i 2 c-bus serial clock input dis 120 i 2 c-bus disable control input symbol pin description
2004 may 18 9 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 tdo 121 scan test output tck 122 scan test mode input; must be connected to ground clp 123 clamp pulse input stbydiv 124 dvi standby output gndd(mcf) 125 mcf digital ground v ccd(mcf) 126 mcf digital supply voltage hsynco 127 horizontal synchronization pulse output deo 128 data enable output hpdo 129 hot plug detector output gndo(ttl) 130 ttl output digital ground v cco(ttl) 131 ttl output digital supply voltage vsynco 132 vertical synchronization pulse output fieldo 133 ?eld information output clpo 134 clamp output ckrefo 135 reference output clock; re-synchronized horizontal negative pulse csynco 136 composite synchronization output acrx2 137 test pin; should be connected to ground acrx1 138 test pin; should be connected to ground gndd(slc) 139 slc digital ground v ccd(slc) 140 slc output digital supply voltage ckext 141 external clock input coast 142 pll coast control input vsync2 143 vertical synchronization pulse input 2 vsync1 144 vertical synchronization pulse input 1 symbol pin description handbook, halfpage mgu896 tda8754hl 109 144 136 108 73 72 37 fig.2 pin configuration lqfp144 package.
2004 may 18 10 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 7.2 lbga208 package symbol ball description sogin1 a1 sync-on-green input 1 gnda(pll) a2 pll analog ground sogin2 a3 sync-on-green input 2 gnda(pll) a4 pll analog ground hsync2 a5 horizontal synchronization pulse input 2 chsync2 a6 composite horizontal synchronization pulse input 2 coast a7 pll coast control input csynco a8 composite synchronization output fieldo a9 ?eld information output hsynco a10 horizontal synchronization pulse output scl a11 i 2 c-bus serial clock input n.c. a12 not connected n.c. a13 not connected dis a14 i 2 c-bus disable control input a0 a15 i 2 c-bus address control input ckdata a16 data clock output gnda(pll) b1 pll analog ground pmo b2 phase measurement output (test) gnda(pll) b3 pll analog ground gnda(pll) b4 pll analog ground v cca(pll) b5 pll analog supply voltage clp b6 clamp pulse input ckext b7 external clock input ckrefo b8 reference output clock; re-synchronized horizontal negative pulse vsynco b9 vertical synchronization pulse output deo b10 data enable output sda b11 i 2 c-bus serial data input and output n.c. b12 not connected n.c. b13 not connected n.c. b14 not connected gndo(clk) b15 clock output digital ground v cco(clk) b16 clock output digital supply voltage rin1 c1 red channel analog input 1 gnda c2 analog ground capsogin1 c3 decoupling sog input 1 capsogin2 c4 decoupling sog input 2 capsogo c5 decoupling sog output hsync1 c6 horizontal synchronization pulse input 1 vsync1 c7 vertical synchronization pulse input 1 clpo c8 clamp output
2004 may 18 11 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 n.c. c9 not connected n.c. c10 not connected tck c11 scan test mode input tdo c12 scan test output v ccd(i2c) c13 i 2 c-bus lines digital supply voltage n.c. c14 not connected n.c. c15 not connected n.c. c16 not connected gnda d1 analog ground gnda d2 analog ground cz d3 pll ?lter input cp d4 pll ?lter input gnda(cpo) d5 cpo analog ground chsync1 d6 composite horizontal synchronization pulse input 1 vsync2 d7 vertical synchronization pulse input 2 hpdo d8 hot plug detector output n.c. d9 not connected n.c. d10 not connected v cco(ttl) d11 ttl output digital supply voltage gndo(ttl) d12 ttl output digital ground gndd(i2c) d13 i 2 c-bus lines digital ground n.c. d14 not connected n.c. d15 not connected n.c. d16 not connected rin2 e1 red channel analog input 2 gnda e2 analog ground gnda e3 analog ground gnda e4 analog ground gndd(ttl) e7 ttl input digital ground v ccd(ttl) e8 ttl input digital supply voltage gndd(slc) e9 slc digital ground v ccd(slc) e10 slc output digital supply voltage n.c. e13 not connected n.c. e14 not connected n.c. e15 not connected n.c. e16 not connected gnda f1 analog ground gnda f2 analog ground rbot f3 red channel ladder decoupling input gnda f4 analog ground n.c. f13 not connected symbol ball description
2004 may 18 12 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 n.c. f14 not connected n.c. f15 not connected n.c. f16 not connected gin1 g1 green channel analog input 1 gnda g2 analog ground dec g3 main regulator decoupling input v cca g4 analog supply voltage v cca g5 analog supply voltage n.c. g12 not connected n.c. g13 not connected n.c. g14 not connected n.c. g15 not connected n.c. g16 not connected gnda h1 analog ground gnda h2 analog ground gnda h3 analog ground rclpc h4 red channel clamp capacitor input v cca h5 analog supply voltage n.c. h12 not connected n.c. h13 not connected n.c. h14 not connected n.c. h15 not connected n.c. h16 not connected gin2 j1 green channel analog input 2 gnda j2 analog ground gbot j3 green channel ladder decoupling input gnda j4 analog ground gclpc j5 green channel clamp capacitor input n.c. j12 not connected n.c. j13 not connected n.c. j14 not connected n.c. j15 not connected n.c. j16 not connected gnda k1 analog ground gnda k2 analog ground gnda k3 analog ground bclpc k4 blue channel clamp capacitor input v cca k5 analog supply voltage n.c. k12 not connected n.c. k13 not connected n.c. k14 not connected symbol ball description
2004 may 18 13 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 n.c. k15 not connected n.c. k16 not connected bin1 l1 blue channel analog input 1 gnda l2 analog ground bbot l3 blue channel ladder decoupling input v cca l4 analog supply voltage n.c. l13 not connected n.c. l14 not connected n.c. l15 not connected n.c. l16 not connected gnda m1 analog ground gnda m2 analog ground agco m3 agc output test m4 test input v cco m7 data output digital supply voltage v cco m8 data output digital supply voltage gndo m9 data output digital ground gndo m10 data output digital ground n.c. m13 not connected n.c. m14 not connected n.c. m15 not connected n.c. m16 not connected bin2 n1 blue channel analog input 2 gnda n2 analog ground gndd(adc) n3 adc digital ground gndd(adc) n4 adc digital ground ba2 n5 blue channel adc output a bit 2 v cco n6 data output digital supply voltage gb4 n7 green channel adc output b bit 4 gb0 n8 green channel adc output b bit 0 ga4 n9 green channel adc output a bit 4 ga0 n10 green channel adc output a bit 0 gndo n11 data output digital ground pwd n12 power-down control input n.c. n13 not connected n.c. n14 not connected n.c. n15 not connected n.c. n16 not connected v ccd(adc) p1 adc digital supply voltage v ccd(adc) p2 adc digital supply voltage bb1 p3 blue channel adc output b bit 1 symbol ball description
2004 may 18 14 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 ba6 p4 blue channel adc output a bit 6 ba3 p5 blue channel adc output a bit 3 bor p6 blue channel adc output bit out of range gb5 p7 green channel adc output b bit 5 gb1 p8 green channel adc output b bit 1 ga5 p9 green channel adc output a bit 5 ga1 p10 green channel adc output a bit 1 rb6 p11 red channel adc output b bit 6 rb3 p12 red channel adc output b bit 3 rb0 p13 red channel adc output b bit 0 ra5 p14 red channel adc output a bit 5 ra2 p15 red channel adc output a bit 2 ror p16 red channel adc output bit out of range bb6 r1 blue channel adc output b bit 6 bb4 r2 blue channel adc output b bit 4 bb2 r3 blue channel adc output b bit 2 ba7 r4 blue channel adc output a bit 7 ba4 r5 blue channel adc output a bit 4 ba0 r6 blue channel adc output a bit 0 gb6 r7 green channel adc output b bit 6 gb2 r8 green channel adc output b bit 2 ga6 r9 green channel adc output a bit 6 ga2 r10 green channel adc output a bit 2 rb7 r11 red channel adc output b bit 7 rb4 r12 red channel adc output b bit 4 rb1 r13 red channel adc output b bit 1 ra6 r14 red channel adc output a bit 6 ra3 r15 red channel adc output a bit 3 ra0 r16 red channel adc output a bit 0 bb7 t1 blue channel adc output b bit 7 bb5 t2 blue channel adc output b bit 5 bb3 t3 blue channel adc output b bit 3 bb0 t4 blue channel adc output b bit 0 ba5 t5 blue channel adc output a bit 5 ba1 t6 blue channel adc output a bit 1 gb7 t7 green channel adc output b bit 7 gb3 t8 green channel adc output b bit 3 ga7 t9 green channel adc output a bit 7 ga3 t10 green channel adc output a bit 3 gor t11 green channel adc output bit out of range rb5 t12 red channel adc output b bit 5 symbol ball description
2004 may 18 15 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 rb2 t13 red channel adc output b bit 2 ra7 t14 red channel adc output a bit 7 ra4 t15 red channel adc output a bit 4 ra1 t16 red channel adc output a bit 1 symbol ball description fig.3 pin configuration lbga208 package. handbook, halfpage a b c d e f h k g j l m n p r t 2468 tda8754el 10 12 14 16 mbl890 13579111315
2004 may 18 16 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 8 functional description this triple high-speed 8-bit adc is designed to convert rgb/yuv signals coming from an analog source into digital data used by a lcd driver (pixel clock up to 270 mhz with analog source) or projections systems. 8.1 power management it is possible to put the tda8754 in standby mode by setting bit stby = 1 or to put the whole device in power- down mode by setting pin pwd to high level. 8.1.1 s tandby mode in standby mode, the status of the blocks is as follows: activity detection, i 2 c-bus slave, sync separator and sog are still active pixel counter, adcs, demultiplexers, agc and clamp cells are inactive output buffers to the rgb block (rgb 0 to 7, ckdata, deo, hsynco and vsynco) are in high-impedance state output hpdo is still active output buffers (ror, bor, gor, ckrefo, csynco, clpo and fieldo) are in a low-level state. 8.1.2 p ower - down mode in power-down mode the status of the blocks is as follows: all digital inputs and outputs are in high-impedance state all blocks are inactive (i 2 c-bus, activity detection, adcs, etc.) analog output is left uncontrolled i 2 c-bus is left in high-impedance state. 8.2 analog video input the rgb/yuv video inputs are externally ac coupled and are internally dc polarized. the synchronization signals are also used by the device as input for the internal pll and the automatic clamp. 8.2.1 a nalog multiplexers the tda8754 has two analog inputs (rgb input 1 and rgb input 2) selectable via the i 2 c-bus. the sync management can be achieved in several ways: choice between two analog inputs hsync and two analog inputs vsync choice between two analog inputs chsync choice between two analog inputs sog. 8.2.2 a ctivity detection when a signal is connected or disconnected on pins hsync1(2), chsync1(2), vsync1(2) and sog1(2), then bit hpdo is set to logic 1 and pin hpdo is set to high to advise the user of a change. bit hpdo is set to logic 0 and pin hpdo is set to low when register activity2 has been read. when the synchronization pulse on pin sog is 3-level, the system will automatically be able to detect that a 3-level sync is present and will force bit 3level to logic 1. it is possible to disable this function with bit ftrilevel. when an interlaced signal is detected, bit acfield is set to logic 1. when the signal detected is progressive, this bit is set to logic 0. any change in this bit results into setting bit hpdo = 1 and pin hpdo = high. a field detection unit is available on pin fieldo which output is given by the sync separator. the field identity is given by pin fieldo. this pin gives the field of interlaced signal input. an automatic polarity detection is also available on pins hsync1(2), vsync1(2) and chsync1(2). the output on pin hpdo is not affected by the change of polarity of these inputs. 8.2.3 adc the three adcs are designed to convert r, g and b (or y, u and v) signals at a maximum frequency of 270 msps. the adc input range is 1 v (p-p) full-scale and the pipeline delay is 2 adc clock cycles from the input sampling to the data output. the reference ladders regulators are integrated.
2004 may 18 17 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 8.2.4 c lamp three independent parallel clamping circuits are used to clamp the video input signals on programmable black levels. the clamp levels may be set from - 24 to +136 lsbs in steps of 1 lsb. they are controlled by three 9-bit i 2 c-bus registers (offsetr, offsetg and offsetb). the clamp pulse can be generated internally (based on the pll clock reference) or can be externally applied on pin clp. by setting correctly the i 2 c-bus bits, it is possible to inhibit the clamp request with the vsync signal. this inhibition will be effected by forcing logic 0 on the clamp request output. it should be noted that the clamp period can start on the falling edge of the clamp request and that the high level of the clamp request sets the adc outputs in the blanking mode. this means that by forcing the clamp signal request to logic 0 by using vsync, a falling edge may happen on the clamp request if this signal was at logic 1 before enforcing the inhibition. to avoid this, the user has to guarantee that the vsync signal used for the clamp inhibition will not be set during a high level of the clamp request signal. remark: if signal vsync is coming from the external pin vsync, this signal may be used to coast the pll. in order to properly do the coast, the edge of signal vsync (coast) must not appear at the same time as the edge of signal hsync. this condition is similar to the pin clp inhibition condition. 8.2.5 agc three independent variable gain amplifiers are used to provide, for each channel, a full-scale input signal to the 8-bit adc. the gain adjustment range is designed in such a way that for an input range varying from 0.5 to 1 v (p-p), the output signal corresponds to the adc full-scale input of 1 v (p-p). 8.3 hsosel, deo and schckrefo bit hsosel allows to have a full correlation phase behaviour between outputs ckdata and hsynco when bit hsosel = 0 (hsync from counter). if hsosel = 0 and bits pa4 to pa0 of register phase are changed to chose the best sampling time, the phase relationship between outputs ckdata and hsynco will stay unchanged. after the video standard is determined, bit hsosel must be set to a logic 0 for normal operation mode. to use the hsync from the counter the registers hsyncl, hbackl, hdisplmsb and hdispllsb should be set properly in order to create the correct hsynco and deo output signals (see figs.5 and 6), which is depending on video standard. output signal deo should be used to determine the first active pixel. the demultiplexed mode should be used (bit dmx = 1) and the output flow is alternated between port a and port b in case the sampling frequency is over 140 msps (clock frequency). it is necessary, in order to warrant that the outputs hsynco and deo are always changing on ckdata output rising edge (see fig.7), that the values hsyncl, hbackl and hdispl (see fig.5) are even value. if an odd value is entered the outputs hsynco and deo can change state during falling edge, which is not compliant with the t h(o) and t d(o) specified output timing. bit schckrefo is used if in demultiplexed mode one pixel shift is needed in the deo signal (to move the screen one vertical line). by setting bit schckrefo from a logic 0 to a logic 1 a left move is obtained, also the timing relationship between hsynco, deo and ckdata stays unchanged. an even number of pixel moves is done by changing the value of hbackl and hsyncl. the correct combination of bits hbackl, hsyncl and schckrefo places the first active pixel at the beginning of the screen with always the correct phase relationship between outputs deo, hsynco and ckdata. bit hsosel should be set to a logic 0 only after the pll is stable, so only after the video standard has been found and correct pll parameters have been set in the tda8754. bit hsosel should be set to a logic 1 to have a stable hsynco signal during the video recognition. the video standard can be recognized by using the signals fieldo, vsynco and hsynco. the phase relation between ckdata and hsynco (or deo) is undefined if bit hsosel = 1. 8.4 pll the adcs are clocked by either the internal pll locked to the reference clock (hsync from input or hsync from sync separator) or to an external clock connected to pin ckext. this selection is performed via the i 2 c-bus by setting bit ckext. to use the external clock, bit ckext must be reset to logic 1. the pll phase frequency detector can be disconnected during the frame flyback (vertical blanking) or the unavailability of the ckref signal by using the coast function. the coast signal can be derived from the vsync1(2) input, from the vsync extracted by the sync separator or from the coast input. the coast function can be disabled with bit coe.
2004 may 18 18 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 the coast signal may be active either high or low by setting bit cos. it is possible to control the phase of the adc clock via the i 2 c-bus with the included digital phase-shift controller. the phase register (5 bits) enables to shift the phase by steps of 11.25 deg. the pll also provides a ckdata clock. this clock is synchronized with the data outputs whatever the output mode is. it is possible to delay the ckdata clock with a constant delay (t = 2 ns compared to the outputs) by setting bit ckdd = 1. moreover, it is possible to invert this output by setting bit ckdatinv = 1. when the pll reference signal comes from the separator, the pll rising edge must be preferably used in order to not use the pll coast mode. it should be noted that the hsynco output of the sync separator is always a mostly low signal, whatever is the polarity of the composite sync input. the vsynco output signal of the sync separator is also mostly low signal. it is at a high state during the vertical blanking. 8.5 sync-on-green when the sog input is selected (bit sogsel = 1), the sog charge pump current bits sogi[1:0] should be programmed in function of the input signal; see table 1. a hum remover is implemented in the sog. it removes completely the hum perturbation on the first or second edge of the horizontal sync pulse for digital video input like vesa, and on the second edge only for analog video input signal like tv or hdtv. the maximum hum perturbation is 250 mv (p-p) at 60 hz to have a correct sog functionality. table 1 charge pump current programming; note 1 note 1. definitions: d tvideo = total time in 2 frames when video signal is strictly superior to black level. d tline = total time of 2 frames. d tsync = total time in 2 frames when the video signal is strictly inferior to black level. bits sogi[1:0] maximum value d tvideo / d tline maximum value d tsync / d tline standard 00 83.5 % 14.8 % tv standards and non-vesa standards 01 86.0 % 12.6 % all tv, hdtv and vesa standards 10 90.5 % 8.6 % hdtv standards or non-vesa standards 11 test mode 8.6 programmable coast when the values of precoast[2:0] = 0 and postcoast[4:0] = 0, the coast pulse equals the vsync input. when an interlaced signal is used, the regenerated coast pulse width may vary from one frame to another of one hsync pulse. in that case, the programmed value of precoast[2:0] needs to be increased by one compared to the expected minimum number of hsync coast pulses before the vertical sync signal. 8.7 data enable this signal qualifies the active data period on the horizontal line. pin deo = high during the active display time and low during the blank time. the start of this signal can be adjusted with bits hsyncl[9:0] and hbackl[9:0]. the length of this signal can be adjusted with bits hdispl[11:0].
2004 may 18 19 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 8.8 sync separator the sync separator is compatible with tv, hdtv and vesa standards. if the green video signal has composite sync on it (sync-on-green), the sog function allows to separate the chsync and the active video part. the chsync signal coming from this sog function is accessible through pin csynco. it is possible to extract the hsync and the vsync signals by using the sync separator from this (c)hsync signal coming from sog or coming from the (c)hsync input. this function is able to get rid of the additional synchronization pulses in vertical blanking like equalization or serration pulses. 8.9 3-level when the synchronization pulse of the input of the sog is 3-level, the system will be able to detect that a 3-level sync is present and will advise the customer if a change is observed by setting bit hpdo = 1 and pin hpdo = high. it is possible to disable this function with bit ftrilevel. when this automatic function is disabled, the manual mode will only influence the separator circuitry. 9i 2 c-bus register description 9.1 i 2 c-bus formats 9.1.1 w rite 1 register each register is programmed independently by giving its subaddress and its data content. table 2 i 2 c-bus sequence for writing 1 register table 3 byte format for writing 1 register sda line description s master starts with a start condition byte 1 master transmits device address (7 bits) plus write command bit (r/ w=0) a slave generates an acknowledge byte 2 master transmits programming mode and subregister address to write to a slave generates an acknowledge byte 3 master transmits data 1 a slave generates an acknowledge p master generates a stop condition bit76543210 byte 1 device address r/ w a6 a5 a4 a3 a2 a1 a0 - 100110x0 byte 2 programming mode register subaddress -- mode sa4 sa3 sa2 sa1 sa0 xx0 ----- byte 3 data 1 d7 d6 d5 d4 d3 d2 d1 d0
2004 may 18 20 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 4 write format bit description 9.1.2 w rite all registers all registers are programmed one after the other, by giving this initial condition (xx11 1111) as the subaddress state; thus, the registers are charged following the predefined sequence of 32 bytes (from subaddress 0 0000 to 1 1111). table 5 i 2 c-bus sequence for writing all registers table 6 byte format for writing all registers bit symbol description byte 1 7 to 1 a[6:0] device address . the tda8754 address is 1001 10x. bit a0 relates with the voltage level on pin a0. 0r/ w write command bit. if r/ w = 0, then write action. byte 2 7 to 6 - not used 5 mode mode selection bit. if mode = 0, then each register can be written independently. 4 to 0 sa[4:0] register subaddress. subaddress of the selected register (from 0 0000 to 1 1111). byte 3 7 to 0 d[7:0] data 1. this value is written in the selected register. sda line description s master starts with a start condition byte 1 master transmits device address (7 bits) plus write command bit (r/ w=0) a slave generates an acknowledge byte 2 master transmits programming mode and subregister address to start writing to a slave generates an acknowledge byte 3 master transmits data 1 a slave generates an acknowledge :: byte 34 master transmits data 32 a slave generates an acknowledge p master generates a stop condition bit76543210 byte 1 device address r/ w a6 a5 a4 a3 a2 a1 a0 - 100110x0 byte 2 programming mode register subaddress -- mode sa4 sa3 sa2 sa1 sa0 xx111111 byte (2 + n) data n d7 d6 d5 d4 d3 d2 d1 d0
2004 may 18 21 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 7 write format bit description 9.1.3 r ead register table 8 i 2 c-bus sequence for reading one register bit symbol description byte 1 7 to 1 a[6:0] device address . the tda8754 address is 1001 10x. bit a0 relates with the voltage level on pin a0. 0r/ w write command bit. if r/ w = 0, then write action. byte 2 7 to 6 - not used 5 mode mode selection bit. if mode = 1, then all registers can be written one after the other. 4 to 0 sa[4:0] register subaddress. initial condition is xx11 1111. byte (2 + n) 7 to 0 d[7:0] data n. this value is written in register 00h + n. sda line description s master starts with a start condition byte 1 master transmits device address (7 bits) plus write command bit (r/ w=0) a slave generates an acknowledge byte 2 master transmits programming mode and subregister address to read from a slave generates an acknowledge byte 3 master transmits read register subaddress a slave generates an acknowledge byte 4 master transmits device address (7 bits) plus read command bit (r/ w=1) a slave generates an acknowledge byte 5 slave transmits data to master a master generates an not-acknowledge after reading the data byte p master generates a stop condition
2004 may 18 22 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 9 byte format for reading register table 10 read format bit description bit76543210 byte 1 device address r/ w a6 a5 a4 a3 a2 a1 a0 - 100110x0 byte 2 programming mode register subaddress -- mode sa4 sa3 sa2 sa1 sa0 xx011111 byte 3 read subaddress ------ ra1 ra0 000000 -- byte 4 device address r/ w a6 a5 a4 a3 a2 a1 a0 - 100110x1 byte 5 data 1 d7 d6 d5 d4 d3 d2 d1 d0 bit symbol description byte 1 7 to 1 a[6:0] device address . the tda8754 address is 1001 10x. bit a0 relates with the voltage level on pin a0. 0r/ w write command bit. if r/ w = 0, then write action. byte 2 7 to 6 - not used 5 mode mode selection bit. if mode = 0, then each register can be written independently. 4 to 0 sa[4:0] register subaddress. subaddress of the read register (1 1111). byte 3 7 to 0 ra[1:0] read address. this is the value of the read register to be selected. byte 4 7 to 1 a[6:0] device address . the tda8754 address is 1001 10x. bit a0 relates with the voltage level on pin a0. 0r/ w read command bit. if r/ w = 1, then read action. byte 5 7 to 0 d[7:0] data 1. the value from read register is sent from the slave to the master.
2004 may 18 23 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 9.2 i 2 c-bus registers overview table 11 i 2 c-bus analog write registers addr name msb bit lsb default value 76 5 4 3 2 1 0 00h offsetr or7 or6 or5 or4 or3 or2 or1 or0 0000 0000 01h coarser or8 cr6 cr5 cr4 cr3 cr2 cr1 cr0 0100 0110 02h finer --- - - fr2 fr1 fr0 xxxx x000 03h offsetg og7 og6 og5 og4 og3 og2 og1 og0 0000 0000 04h coarseg og8 cg6 cg5 cg4 cg3 cg2 cg1 cg0 0100 0110 05h fineg --- - - fg2 fg1 fg0 xxxx x000 06h offsetb ob7 ob6 ob5 ob4 ob3 ob2 ob1 ob0 0000 0000 07h coarseb ob8 cb6 cb5 cb4 cb3 cb2 cb1 cb0 0100 0110 08h fineb --- - - fb2 fb1 fb0 xxxx x000 09h sog do up ftrilevel strilevel ckrefs sogsel sogi1 sogi0 0000 0001 0ah pllctrl ip1 ip0 z2 z1 z0 dr2 dr1 dr0 0101 1100 0bh phase pa4 pa3 pa2 pa1 pa0 vco2 vco1 vco0 0000 0101 0ch divmsb ckext sch ckrefo epsi1 epsi0 di11 di10 di9 di8 0000 0110 0dh divlsb di7 di6 di5 di4 di3 di2 di1 di0 1001 1000 0eh hsyncl hsyncl9 hsyncl8 hsyncl7 hsyncl6 hsyncl5 hsyncl4 hsyncl3 hsyncl2 0010 0100 0fh hbackl hsyncl1 hsyncl0 hbackl9 hbackl8 hbackl7 hbackl6 hbackl5 hbackl4 0000 1111 10h hdisplmsb hbackl3 hbackl2 hbackl1 hbackl0 hdispl11 hdispl10 hdispl9 hdispl8 1000 0101 11h hdispllsb hdispl7 hdispl6 hdispl5 hdispl4 hdispl3 hdispl2 hdispl1 hdispl0 0000 0000 12h coast pre coast2 pre coast1 pre coast0 post coast4 post coast3 post coast2 post coast1 post coast0 0000 0000 13h hsyncsel --- - testcnt bysepa hssel hss xxx x0100 14h vsyncsel --- tstcoast coe vss cossel2 cossel1 xxx0 0000 15h clamp - hsosel clpsel2 clpsel1 clph clpenl iclp clpt x010 0000 16h inverter - cos clps ckrefo inv deo invrgb hso invrgb vso invrgb fieldo inv x000 0000 17h output rgbsel ten agcsel1 agcsel0 blken dmxrgb oddargb shiftrgb 0000 0000 18h outputen1 --- boenrgb aoenrgb oroen toutergb toutsrgb xxx1 1100
2004 may 18 24 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 12 i 2 c-bus analog read registers; note 1 note 1. the read register address is specified with bits addr1 and addr0 of register readaddr. 19h outputen2 ckroen csoen deoen rgb hsoen rgb hpdoen vsoen rgb clpoen fieldoen 1111 1111 1ah clkoutput --- cksel rgb dlyclk rgb ckdat inv out oscill ckoen rgb xxx0 0001 1bh intosc --- - - - switch osc intosc off xxxx xx00 1ch reserved 1dh reserved 1eh pwrmgt --- - shckdmx shckadc stby dvirgb xxxx 0000 1fh readaddr --- - - - addr1 addr0 xxxx xx00 addr name msb bit lsb default value 76 5 4 3 2 1 0 1 version --- - ver3 ver2 ver1 ver0 xxxx 0000 2 sign -- polvs2 polvs1 polchs2 polchs1 polhs2 polhs1 xx00 0000 3 activity1 acvs2 acvs1 acsog2 acsog1 acchs2 acchs1 achs2 achs1 0000 0000 4 activity2 - asd 3level acfield hpdo acvssep acrxc1 acrxc0 x000 0000 addr name msb bit lsb default value 76 5 4 3 2 1 0
2004 may 18 25 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.3 offset registers (r, g and b) the offset registers contain a 9-bit value which controls the clamp level for the rgb channels. the 8 lsbs are in the offset registers and the 1 msb is in the coarse gain control register. the relationship between the programming code and the level of the clamp code is given in table 15. the default value is: clamp code = 0 and adc output = 0. table 13 offset registers (00h, 03h, 06h) bit allocation table 14 offset registers (00h, 03h, 06h) bit description table 15 coding for clamp level and adc output register 76543210 offsetr (00h) or7 or6 or5 or4 or3 or2 or1 or0 offsetg (03h) og7 og6 og5 og4 og3 og2 og1 og0 offsetb (06h) ob7 ob6 ob5 ob4 ob3 ob2 ob1 ob0 default 00000000 bit symbol description offsetr (address: 00h) 7 to 0 or[7:0] offset r channel; lsb in this register and msb bit or8 in register coarser offsetg (address: 03h) 7 to 0 og[7:0] offset g channel; lsb in this register and msb bit og8 in register coarseg offsetb (address: 06h) 7 to 0 ob[7:0] offset b channel; lsb in this register and msb bit ob8 in register coarseb hex value or8 or7 or6 or5 or4 or3 or2 or1 or0 clamp code (decimal) adc output (code transition) og8 og7 og6 og5 og4 og3 og2 og1 og0 ob8 ob7 ob6 ob5 ob4 ob3 ob2 ob1 ob0 1e9 111101000 - 24 - 24/ - 23 1ea 111101001 - 23 - 23/ - 22 : :: 1ff 111111111 - 1 - 1/0 000 000000000 0 0/1 001 000000001 +1 1/2 : :: 03f 000111111 63 63/64 040 001000000 64 64/65 : :: 078 001111000 120 120/121 079 001111001 121 121/122 : :: 080 010000000 128 128/129
2004 may 18 26 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.4 coarse registers (r, g and b) the coarse gain of the agc is controlled with 7 bits. the code gain can vary from 32 to 95; see table 18. table 16 coarse gain registers (01h, 04h, 07h) bit allocation table 17 coarse gain registers (01h, 04h, 07h) bit description table 18 coarse register : :: 086 010000110 134 134/135 087 010000111 135 135/136 register 76543210 coarser (01h) or8 cr6 cr5 cr4 cr3 cr2 cr1 cr0 coarseg (04h) og8 cg6 cg5 cg4 cg3 cg2 cg1 cg0 coarseb (07h) ob8 cb6 cb5 cb4 cb3 cb2 cb1 cb0 default 01000110 bit symbol description coarser (address: 01h) 7 or8 offset r channel; msb bit of offset value 6 to 0 cr[6:0] coarse gain of the agc for r channel coarseg (address: 04h) 7 og8 offset g channel; msb bit of offset value 6 to 0 cg[6:0] coarse gain of the agc for g channel coarseb (address: 07h) 7 ob8 offset b channel; msb bit of offset value 6 to 0 cb[6:0] coarse gain of the agc for b channel decimal value cr6 cr5 cr4 cr3 cr2 cr1 cr0 v i to be full-scale gain adc cg6 cg5 cg4 cg3 cg2 cg1 cg0 cb6 cb5 cb4 cb3 cb2 cb1 cb0 32 0100000 1.000 1.000 33 0100001 0.992 1.008 ::: 63 0111111 0.753 1.328 64 1000000 0.746 1.340 65 1000001 0.738 1.355 ::: hex value or8 or7 or6 or5 or4 or3 or2 or1 or0 clamp code (decimal) adc output (code transition) og8 og7 og6 og5 og4 og3 og2 og1 og0 ob8 ob7 ob6 ob5 ob4 ob3 ob2 ob1 ob0
2004 may 18 27 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.5 fine registers (r, g and b) fine gain control is done with 3 bits allowing 8 intermediate values between two values of consecutive coarse gain. table 19 fine gain registers (02h, 05h, 08h) bit allocation table 20 fine gain registers (02h, 05h, 08h) bit description table 21 fine gain control bits (example for coarse register value 32) 69 1000101 0.706 1.416 70 1000110 0.698 1.432 ::: 95 1011111 0.500 2.000 register 76543210 finer (02h) ----- fr2 fr1 fr0 fineg (05h) ----- fg2 fg1 fg0 fineb (08h) ----- fb2 fb1 fb0 default x x x x x 0 0 0 bit symbol description finer (address: 02h) 7 to 3 - not used 2 to 0 fr[2:0] ?ne gain of the agc for r channel fineg (address: 05h) 7 to 3 - not used 2 to 0 fg[2:0] ?ne gain of the agc for g channel fineb (address: 08h) 7 to 3 - not used 2 to 0 fb[2:0] ?ne gain of the agc for b channel decimal value fr2 fr1 fr0 fine steps of gain adc fg2 fg1 fg0 fb2 fb1 fb0 0 0 0 0 1.000 1 0 0 1 1.001 2 0 1 0 1.002 3 0 1 1 1.003 4 0 0 0 1.004 decimal value cr6 cr5 cr4 cr3 cr2 cr1 cr0 v i to be full-scale gain adc cg6 cg5 cg4 cg3 cg2 cg1 cg0 cb6 cb5 cb4 cb3 cb2 cb1 cb0
2004 may 18 28 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.6 sog register table 22 sog (09h) bit allocation table 23 sog (09h) bit description 5 0 0 1 1.005 6 0 1 0 1.006 7 1 1 1 1.007 bit76 5 4 3210 symbol do up ftrilevel strilevel ckrefs sogsel sogi1 sogi0 default 0 0 0 0 0001 bit symbol description 7 do test bit for forcing charge pump current down 0 = default value 1 = forcing down 6 up test bit for forcing charge pump current up 0 = default value 1 = forcing up 5 ftrilevel de?nes the 3-level function mode 0 = automatic 3-level 1 = level selection with bit strilevel 4 strilevel forces the state of 3-level function 0 = not 3-level mode 1 = 3-level mode 3 ckrefs enables the pll ckref signal to be selected 0 = same as input 1 = input inverted 2 sogsel enables the reference pll between hsync input and sog input to be selected 0 = hsync input 1 = sog input 1 to 0 sogi[1:0] de?nes the sog charge pump current; values are given in % of sync pulse/line length 00 = 14.8 % maximum (tv standards) and non-vesa standards 01 = 12.6 % maximum (all standards) 10 = 8.6 % maximum (hdtv standards) and non-vesa standards 11 = 0 test mode decimal value fr2 fr1 fr0 fine steps of gain adc fg2 fg1 fg0 fb2 fb1 fb0
2004 may 18 29 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.7 pll control table 24 pllctrl (0ah) bit allocation table 25 pllctrl (0ah) bit description 9.8 phase register table 26 phase (0bh) bit allocation table 27 phase (0bh) bit description bit76543210 symbol ip1 ip0 z2 z1 z0 dr2 dr1 dr0 default 01011100 bit symbol description 7 to 6 ip[1:0] charge pump current value to increase the bandwidth of the pll 00 = 800 m a 01 = 1200 m a 10 = 1600 m a 11 = 2000 m a 5 to 3 z[2:0] internal resistance value for the vco ?lter to be selected 000 = not used 001 = 1.56 k w 010 = 1.25 k w 011 = 1.00 k w 100 = 0.80 k w 101 = 0.64 k w 110 = 0.51 k w 111 = 0.41 k w 3 to 0 dr[2:0] pll temperature phase drift to be compensated. the optimized value of this register is 001. these bits add a delay on the clock reference input of the pll as a function of the temperature of the die. 000 = +1.75 step phase 001 = - 0.3 step phase 010 = - 4.3 step phase 011 = - 6.2 step phase 100 = - 2.2 step phase bit76543210 symbol pa4 pa3 pa2 pa1 pa0 vco2 vco1 vco0 default 00000101 bit symbol description 7 to 4 pa[4:0] phase shift value for the clock pixel. see table 28. 3 to 0 vco[2:0] vco gain control. see table 29.
2004 may 18 30 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 28 phase registers bits table 29 vco gain control 9.9 pll divider registers table 30 divmsb (0ch) bit allocation table 31 divmsb (0ch) bit description pa4 pa3 pa2 pa1 pa0 phase shift (deg) 00000 0 00001 11.25 ::::: : 11110 337.50 11111 348.75 vco2 vco1 vco0 vco gain (mhz/v) pixel clock frequency (mhz) 0 0 0 13 12 to 22 0 0 1 30 22 to 45 0 1 0 60 45 to 62 0 1 1 60 62 to 85 1 0 0 105 85 to 120 1 0 1 105 120 to 176 1 1 0 135 176 to 270 1 1 1 no oscillation - bit76543210 symbol ckext sch ckrefo epsi1 epsi0 di11 di10 di9 di8 default 00000110 bit symbol description 7 ckext external clock selection 0 = internal pll 1 = external clock 6 sch ckrefo shift of pixel counter reference (ckref) with one clock pixel period 0 = not active 1 = active 5 to 4 epsi[1:0] enables the resynchronization edge of ckrefo to be selected; they are test bits 00 = default value for proper operation 3 to 0 di[11:8] pll divider ratio. these are the 4 msbs of the 12-bit value. see table 34.
2004 may 18 31 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 32 divlsb (0dh) bit allocation table 33 divlsb (0dh) bit description table 34 pll divider ratio 9.10 horizontal sync registers remark: the sum of hsyncl[9:0] + hbackl[9:0] + hdispl[9:0] + 16 needs to be smaller than the pll divider. table 35 hsyncl, hbackl and hdispl bits allocation table 36 sync registers (0eh to 11h) bit description bit76543210 symbol di7 di6 di5 di4 di3 di2 di1 d0 default 1 0 0 1 1 0 0 0 bit symbol description 7 to 0 di[7:0] pll divider ratio. these are the 8 lsbs of the 12-bit value. see table 34. di11 di10 di9 di8 di7 di6 di5 di4 di3 di2 di1 di0 pll divider ratio 000001100100 100 :::::::::::: : 111111111111 4095 bit76543210 register address 0eh symbol hsyncl9 hsyncl8 hsyncl7 hsyncl6 hsyncl5 hsyncl4 hsyncl3 hsyncl2 default 0 0 1 0 0 1 0 0 register address 0fh symbol hsyncl1 hsyncl0 hbackl9 hbackl8 hbackl7 hbackl6 hbackl5 hbackl4 default 0 0 0 0 1 1 1 1 register address 10h symbol hbackl3 hbackl2 hbackl1 hbackl0 hdispl11 hdispl10 hdispl9 hdispl8 default 1 0 0 0 0 1 0 1 register address 11h symbol hdispl7 hdispl6 hdispl5 hdispl4 hdispl3 hdispl2 hdispl1 hdispl0 default 0 0 0 0 0 0 0 0 bit symbol description - hsyncl[9:0] length of the hsync signal; in number of pixel clock cycles; minimum value is 16 - hbackl[9:0] interval between the hsync active edge and the ?rst active pixel; in number of pixels; minimum value is 16 - hdispl[11:0] number of active pixels for one line; length of the data enable signal; minimum value is 16
2004 may 18 32 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.11 coast register remark: when postcoast[4:0] = precoast[2:0] = 0, then the coast pulse equals the vsync input. table 37 coast (12h) bit allocation table 38 coast (12h) bit description 9.12 horizontal sync selection register table 39 hsyncsel (13h) bit allocation table 40 hsyncsel (13h) bit description bit76543210 symbol pre coast2 pre coast1 pre coast0 post coast4 post coast3 post coast2 post coast1 post coast0 default 00000000 bit symbol description 7 to 5 pre coast[2:0] programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the vertical sync signal 4 to 0 post coast[4:0] programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the vertical sync signal bit76543210 symbol ---- testcnt bysepa hssel hss default x x x x 0 1 0 0 bit symbol description 7 to 4 - not used 3 testcnt this bit is used to test the pixel counter 0 = normal mode 1 = test mode 2 bysepa enables the sync separator for the pll reference to be bypassed 0 = hsync from the separator 1 = bypass of the sync separator 1 hssel enables either the hsync or chsync input signal to be selected 0 = hsync input 1 = chsync input 0 hss enables either the hsync or chsync input signal to be inverted 0 = non-inverted 1 = inverted
2004 may 18 33 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.13 vertical sync selection register table 41 vsyncsel (14h) bit allocation table 42 vsyncsel (14h) bit description 9.14 clamp register table 43 clamp (15h) bit allocation table 44 clamp (15h) bit description bit7654321 0 symbol --- tstcoast coe vss cossel2 cossel1 default x x x 0 0 0 0 0 bit symbol description 7 to 5 - not used 4 tstcoast switches a multiplexer to select the output signal on pin vsynco 0 = output of the separator function 1 = output of the coast function 3 coe enables coast mode 0 = coast mode 1 = no coast mode 2 vss enables vsync input signal to be inverted 0 = non-inverted 1 = inverted 1 cossel2 selects signal for coast pll mode 0 = signal selected with bit cossel1 1 = pin coast 0 cossel1 can be used for the coast pll mode; see bit cossel2 0 = vsync input 1 = vsync from the sync separator bit765 43210 symbol - hsosel clpsel2 clpsel1 clph clpenl iclp clpt default x 0 1 00000 bit symbol description 7 - not used 6 hsosel de?nes the signal on the output hsynco; see section 8.3 0 = hsync from the hcounter 1 = ckref is reference of the pll 5 clpsel2 can be used to select the clamp signal 0 = hsync signal generated by the pixel counter 1 = signal selected with bit clpsel1
2004 may 18 34 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.15 inverter register table 45 inverter (16h) bit allocation table 46 inverter (16h) bit description 4 clpsel1 can be used to select the clamp signal; see bit clpsel2 0 = pll reference signal 1 = clamp input 3 clph inhibits the clamp signal during the vsynco or coast signal; see bit tstcoast (table 42) 0 = clamp inhibited during vsynco 1 = clamp active during vsynco 2 clpenl de?nes if clamp input works on edge or on level 0 = on edge; for all frequencies (must be preferably chosen) 1 = on level; only for frequencies below 45 mhz to have proper clamp function 1 iclp dedicated for test mode; should be forced to logic 0 0 clpt de?nes if the test mode of the clamp is active 0 = not active 1 = active bit7 6543210 symbol - cos clps ckrefo inv deoinv rgb hsoinv rgb vsoinv rgb fieldo inv default x 0 0 0 0 0 0 0 bit symbol description 7 - not used 6 cos enables the coast input signal to be inverted 0 = non-inverted 1 = inverted 5 clps enables the clamp input signal to be inverted 0 = non-inverted 1 = inverted 4 ckrefoinv enables the output ckrefo to be inverted 0 = non-inverted 1 = inverted 3 deoinvrgb enables the output deo to be inverted 0 = non-inverted 1 = inverted 2 hsoinvrgb enables the output hsynco to be inverted 0 = non-inverted 1 = inverted bit symbol description
2004 may 18 35 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.16 output register table 47 output (17h) bit allocation table 48 output (17h) bit description 1 vsoinvrgb enables the output vsynco to be inverted 0 = non-inverted 1 = inverted 0 fieldoinv enables the output fieldo to be inverted 0 = non-inverted 1 = inverted bit7 65 4 3210 symbol rgbsel ten agcsel1 agcsel0 blken dmxrgb oddargb shiftrgb default 0 0 0 0 0000 bit symbol description 7 rgbsel de?nes which rgb input will be used 0 = input 1 1 = input 2 6 ten enables the track and hold operating mode to be selected 0 = mode enable; must be set to logic 0 for proper operation 1 = mode disable 5 to 4 agcsel[1:0] de?ne the output on pin agco 00 = ragc 01 = gagc 10 = bagc 11 = not used 3 blken inhibits the blanking mode during clamp 0 = blanking active; during the blanking period, the rgb outputs of the adc are fixed at the values of registers offsetr, offsetg and offsetb if these values are greater or equal to 0, or forced to 0 if these values are negative. 1 = blanking not active 2 dmxrgb determines whether all pixels go to port a or if pixels go alternately to port a and b. the maximum data rate for single port mode is 140 mhz and it is 270 mhz in dual port mode. 0 = port a 1 = port a and b 1 oddargb de?nes the parity of the pixels 0 = even pixel on port a 1 = odd pixel on port a 0 shiftrgb de?nes output on port a and b 0 = synchronous 1 = interleaved bit symbol description
2004 may 18 36 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.17 output enable register 1 table 49 outputen1 (18h) bit allocation table 50 outputen1 (18h) bit description 9.18 output enable register 2 table 51 outputen2 (19h) bit allocation table 52 outputen2 (19h) bit description bit76543210 symbol --- boenrgb aoenrgb oroen toutergb toutsrgb default x x x 11100 bit symbol description 7 to 5 - not used 4 boenrgb enables output port b to be set to high-impedance 0 = active signal 1 = high-impedance 3 aoenrgb enables output port a to be set to high-impedance 0 = active signal 1 = high-impedance 2 oroen enables outputs out of range to be set to high-impedance 0 = active signal 1 = high-impedance 1 toutergb de?nes if the test mode of the output buffer is active or not 0 = mode normal 1 = mode test 0 toutsrgb de?nes the state of the output in test mode 0 = forces output to low 1 = forces output to high bit765 43210 symbol ckroen csoen deoenrgb hsoenrgb hpdoen vsoenrgb clpoen fieldoen default 1 1 1 11111 bit symbol description 7 ckroen enables the output ckrefo to be set to high-impedance 0 = active signal 1 = high-impedance 6 csoen enables the output csynco to be set to high-impedance 0 = active signal 1 = high-impedance
2004 may 18 37 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.19 clock output register table 53 clkoutput (1ah) bit allocation table 54 clkoutput (1ah) bit description 5 deoenrgb enables the output deo to be set to high-impedance 0 = active signal 1 = high-impedance 4 hsoenrgb enables the output hsynco to be set to high-impedance 0 = active signal 1 = high-impedance 3 hpdoen enables the output hpdo to be set to high-impedance 0 = active signal 1 = high-impedance 2 vsoenrgb enables the output vsynco to be set to high-impedance 0 = active signal 1 = high-impedance 1 clpoen enables the output clpo to be set to high-impedance 0 = active signal 1 = high-impedance 0 fieldoen enables the output fieldo to be set to high-impedance 0 = active signal 1 = high-impedance bit76543210 symbol --- ckselrgb dlyclkrgb ckdatinv outoscill ckoenrgb default x x x 00001 bit symbol description 7 to 5 - not used 4 ckselrgb enables the selection of the signal on the pin ckdata 0 = clock of output buffers; signal ckdata 1 = pixel clock of the converter; signal ckadco 3 dlyclkrgb enables a delay of 2 ns to be added to the clock ckdata 0 = no delay 1 = 2 ns delay 2 ckdatinv enables the polarity of the output ckdata to be inverted 0 = non-inverted 1 = inverted 1 outoscill enables pin ckdata to be switched with a multiplexer to have signal ckdata or the internal oscillator on the output 0 = ckdata 1 = for test bit symbol description
2004 may 18 38 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.20 internal oscillator register table 55 intosc (1bh) bit allocation table 56 intosc (1bh) bit description 9.21 power management register table 57 pwrmgt (1eh) bit allocation table 58 pwrmgt (1eh) bit description 0 ckoenrgb enables the output ckdata to be set to high-impedance 0 = active signal 1 = high-impedance bit765432 1 0 symbol ------ switchosc intoscoff default xxxxxx 0 0 bit symbol description 7 to 2 - not used 1 switchosc enables a multiplexer to be switched; signal insertion on the input of the separator and coast block, between the internal oscillator and pin ckext 0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = test mode 0 intoscoff disables the internal oscillator for the separator function, the coast gate and activity detection 0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = disabled bit76543210 symbol ---- shckdmx shckadc stby dvirgb default x x x x 0 0 0 0 bit symbol description 7 to 4 - not used 3 shckdmx test bits; should be set to logic 0 for proper operation 2 shckadc test bits; should be set to logic 1 for better performances 1 stby enables the rgb block to be forced into the standby mode, except activity detection, i 2 c-bus registers. in the standby mode, all outputs are in high-impedance state, except pin hpdo which is still active. if the ic is in the power-down mode, this bit has no effect 0 = ic active 1 = standby mode 0 dvirgb this bit must be set to logic 0 for proper operation bit symbol description
2004 may 18 39 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.22 read register table 59 readaddr (1fh) bit allocation table 60 readaddr (1fh) bit description 9.23 version register table 61 version (01h) bit allocation table 62 version (01h) bit description bit76543210 symbol ------ addr1 addr0 default xxxxxx0 0 bit symbol description 7 to 2 - not used 1 to 0 addr[1:0] register address to be read 00 = read register 0 01 = read register 1 10 = read register 2 11 = read register 3 bit76543210 symbol ---- ver3 ver2 ver1 ver0 default xxxx 0000 bit symbol description 7 to 4 - not used 3 to 0 ver[3:0] version of the ic
2004 may 18 40 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.24 sign detection register the sign bits are set at logic 0 when the input is a mostly low input signal. table 63 sign bit allocation table 64 sign bit description bit76543210 symbol -- polvs2 polvs1 polchs2 polchs1 polhs2 polhs1 default x x 0 0 0 0 0 0 bit symbol description 7 to 6 - not used 5 polvs2 sign of vsync2 input 0 = non inverted 1 = inverted 4 polvs1 sign of vsync1 input 0 = non inverted 1 = inverted 3 polchs2 sign of chsync2 input 0 = non inverted 1 = inverted 2 polchs1 sign of chsync1 input 0 = non inverted 1 = inverted 1 polhs2 sign of hsync2 input 0 = non inverted 1 = inverted 0 polhs1 sign of hsync1 input 0 = non inverted 1 = inverted
2004 may 18 41 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.25 activity detection register 1 table 65 activity1 bit allocation table 66 activity1 bit description bit76543210 symbol acvs2 acvs1 acsog2 acsog1 acchs2 acchs1 achs2 achs1 default 00000000 bit symbol description 7 acvs2 activity of vsync2 input 0 = not active 1 = active 6 acvs1 activity of vsync1 input 0 = not active 1 = active 5 acsog2 activity of sogin2 input 0 = not active 1 = active 4 acsog1 activity of sogin1 input 0 = not active 1 = active 3 acchs2 activity of chsync2 input 0 = not active 1 = active 2 acchs1 activity of chsync1 input 0 = not active 1 = active 1 achs2 activity of hsync2 input 0 = not active 1 = active 0 achs1 activity of hsync2 input 0 = not active 1 = active
2004 may 18 42 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 9.26 activity detection register 2 it should be noted that activity, sign and polarity detection will be correctly set after a maximum delay of: 6 frame periods + 50 ms. table 67 activity2 bit allocation table 68 activity2 bit description bit76543210 symbol - asd 3level acfield hpdo acvssep acrxc1 acrxc0 default x 0000000 bit symbol description 7 - not used 6 asd indicates if parasite sync pulses have been detected 0 = not detected 1 = detected 5 3level state of the sync separator input 0 = hsync 1 = 3-level hsync 4 acfield activity of the sync separator fieldo output 0 = not active 1 = active 3 hpdo copy of the hpdo output state 0 = stable state on input 1 = new input 2 acvssep activity of the sync separator (vsync output) 0 = not active 1 = active 1 acrxc1 test bit 0 acrxc0 test bit
2004 may 18 43 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 10 limiting values in accordance with the absolute maximum rating system (iec 60134). 11 thermal characteristics 12 characteristics typical values are measured at v cca =v cca(sog) to gnda(sog) or v cca(r) to gnda(r) or v cca(g) to gnda(g) or v cca(b) to gnda(b) = 3.3 v; v ccd =v ccd(ttl) to gndd(ttl) or v ccd(adc) to gndd(adc) or v ccd(i2c) to gndd(i2c) or v ccd(mcf) to gndd(mcf) or v ccd(ttl) to gndd(ttl) or v ccd(slc) to gndd(slc) = 3.3 v; v cco =v cco(bb) to gndo(bb) or v cco(ba) to gndo(ba) or v cco(gb) to gndo(gb) or v cco(ga) to gndo(ga) or v cco(rb) to gndo(rb) or v cco(ra) to gndo(ra) or v cco(clk) to gndo(clk) = 3.3 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +5 v d v cc supply voltage differences - 0.5 +0.5 v v i input voltage referred to gnda - 0.5 +4.5 v v i(scl,sda) i 2 c-bus input voltage referred to gndd - 0.5 +6.5 v i o output current - 50 ma t stg storage temperature - 55 +150 c t amb ambient temperature 0 70 c t j junction temperature - 150 c v esd electrostatic discharge voltage hbm, lqfp144 package - 3000 +3000 v symbol parameter conditions min. typ. max. unit r th(j-a) thermal resistance from junction to ambient, jedec4l in free air lqfp144 package - 35 - c/w lbga208 package - 30 - c/w r th(j-c) thermal resistance from junction to case lqfp144 package - 8.1 8.5 c/w symbol parameter conditions min. typ. max. unit supplies v cca analog supply voltage 3.0 3.3 3.6 v v ccd digital supply voltage 3.0 3.3 3.6 v v cco output stage supply voltage 3.0 3.3 3.6 v i cca analog supply current - 180 - ma i ccd digital supply current - 125 - ma i cco output stage supply current - 1 - ma d v cc supply voltage difference v cca to v ccd - 100 - +100 mv v cco to v ccd - 165 - +165 mv v cca to v cco - 165 - +165 mv
2004 may 18 44 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 p tot total power dissipation - 1.0 1.3 w p power dissipation power-down mode - 10 - mw standby mode - 120 - mw r, g and b ampli?ers rgb inputs : pins rin1, gin1, bin1, rin2, gin2 and b in 2 v i(p-p) input voltage range (peak-to-peak value) 0.5 - 1.0 v i i input current - 40 - +40 m a c i input capacitance - 3 - pf r i input resistance 50 -- k w a mplifiers b bandwidth - 3 db; t amb =25 c - 700 - mhz g c coarse gain minimum coarse gain; code = 32 - 0 - db maximum coarse gain; code = 95 - 6 - db d g/ d t ampli?er gain stability variation with temperature minimum coarse gain; code = 32 - 2 - % g e(rms) full-scale channel-to-channel matching (rms value) minimum coarse gain; code = 32 -- 2.5 % r, g and b clamp n clamp clamp level accuracy f clk = 25mhz, clamp code = 20 -- 1 lsb phase-locked loop (pll) pll; see table 69 j pll(p-p) long term pll phase jitter (peak-to-peak value) f clk = 270 mhz; dr = 2160 - 390 480 ps dr divider ratio 100 - 4095 f pll output clock frequency 10 - 270 mhz f ref reference clock frequency 15 - 150 khz dj step phase drift -- 2 step j step phase shift step - 11.25 - deg analog-to-digital converters (adcs) ; minimum coarse gain f s(max) maximum sampling frequency 270 -- mhz inl integral non-linearity f clk = 270 mhz; f i = 10 mhz - 0.6 1.3 lsb dnl differential non-linearity f clk = 270 mhz; f i = 10 mhz - 0.25 0.6 lsb enob effective number of bits f clk = 270 mhz; f i = 10 mhz - 7.6 - bits a ct crosstalk f clk = 270 mhz --- 45 db s/n signal-to-noise ratio f clk = 270 mhz; f i = 10 mhz - 48 - db sfdr spurious free dynamic range f clk = 270 mhz; f i = 10 mhz 48 55 - db thd total harmonic distortion f clk = 270 mhz; f i = 10 mhz - -55 - 48 db symbol parameter conditions min. typ. max. unit
2004 may 18 45 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 data timing ; 10 pf load; see fig.4 t d(o) output delay - 4 5.2 ns t h(o) output hold time 1.9 -- ns t su(o) output setup time -- 6ns lv-ttl digital inputs and outputs i nput pins ckext, coast, vsync1, vsync2, hsync1, hsync2, chsync1, chsync2, pwd, a0, dis, tck and clp v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.0 - v ccd v output pins ra[7:0], rb[7:0], ga[7:0], gb[7:0], ba[7:0], bb[7:0], ror, bor, gor, ckdata, tdo, deo, hpdo, hsynco, vsynco, fieldo, clpo, ckrefo and csynco v ol low-level output voltage i oh =1ma -- 0.4 v v oh high-level output voltage i ol = - 1 ma 2.4 -- v data clock output output pin ckdata f ckdata(max) maximum buffer frequency - 140 - mhz data outputs output pins ra[7:0], rb[7:0], ga[7:0], gb[7:0], ba[7:0], bb[7:0], ror, bor, gor, deo, hsynco and csynco f data(max) maximum buffer frequency - 70 - mhz hsync inputs i nput pins hsync1, hsync2, chsync1 and chsync2 t w(hsync)(min) minimum pulse width 250 -- ns t w(hsync)(max) maximum pulse width in % of total horizontal line -- 20 % sog inputs i nput pins sogin1 and sogin2 v sync(g) sync-on-green pulse amplitude 150 -- mv v sync(g) high/low differential amplitude of 3-level pulse -- 20 % i 2 c-bus (fast mode; 5 v tolerant) p ins scl and sda f scl clock frequency -- 400 khz v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.0 - 5.5 v c b capacitive load -- 400 pf thermal characteristics r th(j-c) thermal resistance from junction to case lqfp144 package - 8.1 8.5 c/w symbol parameter conditions min. typ. max. unit
2004 may 18 46 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 table 69 examples of pll settings and performance v cca =v ccd =v cco = 3.3 v; t amb =25 c; note 1. note 1. pll long-term time jitter is measured at the end of the video line, where it is at its maximum. video standard f ref (khz) f clk (mhz) dr k o (mhz/v) c z (nf) c p (pf) i p ( m a) z ( w ) long-term time jitter rms (ps) p-p (ps) vga 60 hz 31.469 25.175 800 30 220 680 1200 510 500 3000 vesa: 640 480 svga 72 hz 48.08 50 1040 60 220 680 1200 510 370 1980 vesa: 800 600 xga 75 hz 60.02 78.75 1312 60 220 680 1600 640 220 1320 vesa: 1024 768 sxga 60 hz 63.98 108 1688 105 220 680 1600 510 185 1110 vesa: 1280 1024 sxga 75 hz 80.00 135 1688 105 220 680 1600 640 145 870 vesa: 1280 1024 uxga 60 hz 75.00 162 2160 105 220 680 2000 640 135 810 vesa: 1600 1200 uxga 75 hz 93.75 202.5 2160 135 220 680 1600 800 95 570 vesa: 1600 1200 uxga 85 hz 106.25 229.5 2160 135 220 680 2000 640 85 510 vesa: 1600 1200 ckdata mce410 50 % 50 % sample n sample n + 1 sample n + 2 rgb input rgb outputs a7 to a0, b7 to b0, deo, hsynco, ckrefo t h(o) v oh v ol v oh v ol t su t d(o) data n - 1 data n - 2 data n + 1 data n fig.4 data timing diagram.
2004 may 18 47 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 13 timing h andbook, full pagewidth mdb107 possibility to add a clock period with bit schckrefo 1234 hs hb hb - 11 1 hs - 1hs - 2hdhd - 1hd - 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 12345678910111213141516171819202122232425262728 27 28 1 2 3 4 r,g,b in cs ckdivo ckphi ckrefin hcount hsyncin dein ckadco adc out hsyncl hbackl hdispl j fig.5 timing diagram. hsyncl, hbackl and hdispl must be long 16 (minimum value in number of pixel clock cycles).
2004 may 18 48 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 fig.6 output format port a. hscynco, deo, ckrefo and rgb outputs a7 to a0 are referred to the rising edge of ckrefin. ckrefo is low during 8 clock pulses. handbook, full pagewidth mdb201 ckrefin ckrefo hsynco deo ckdata 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 rgb outputs a7 to a0 handbook, full pagewidth mdb108 ckrefin ckrefo deo ckdata 28 2 4 6 8 10 12 14 16 18 28 2 4 6 8 10 12 14 16 18 27 1 3 5 7 9 11 13 15 17 27 1 3 5 7 9 11 13 hsynco 15 17 19 bit shiftrgb = 0 bit shiftrgb = 1 rgb outputs a7 to a0 rgb outputs b7 to b0 rgb outputs a7 to a0 rgb outputs b7 to b0 fig.7 output formats ports a and b; even pixels port a and odd pixels port b. hsynco, deo, ckrefo and rgb outputs a7 to a0 are referred to the rising edge of ckrefin. ckrefo is low during 8 clock pulses.
2004 may 18 49 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 handbook, full pagewidth mdb200 ckrefin ckrefo hsynco deo ckdata 28 2 4 6 8 10 12 14 16 18 27 1 3 5 7 9 11 13 15 17 bit shiftrgb = 0 rgb outputs a7 to a0 rgb outputs b7 to b0 fig.8 output formats ports a and b; odd pixels port a; bit shiftrgb = 0. hsynco, deo, ckrefo and rgb outputs a7 to a0 are referred to the rising edge of ckrefin. ckrefo is low during 8 clock pulses. handbook, full pagewidth mce411 ckrefin ckrefo hsynco deo ckdata rgb outputs a7 to a0 rgb outputs b7 to b0 28 2 4 6 8 10 12 14 16 18 271357911131517 bit shiftrgb = 1 fig.9 output formats ports a and b; odd pixels port a; bit shiftrgb = 1. hsynco, deo, ckrefo and rgb outputs a7 to a0 are referred to the rising edge of ckrefin. ckrefo is low during 8 clock pulses.
2004 may 18 50 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 14 application information handbook, full pagewidth mdb109 1 gndd(ttl) v ccd(ttl) hsync2 chsync2 v cca(pll) hsync1 chsync1 gnda(pll) cz gnda(cpo) cp pmo gnda(sub) capsogin1 capsogo capsogin2 gnda(sog) sogin1 v cca(sog) sogin2 v cca(r) rin1 gnda(r1) rin2 gnda(r2) dec rbot rclpc v cca(g) gin1 gnda(g1) gin2 gnda(g2) gbot gclpc v cca(b) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 ra6 ra5 ra4 ra3 ra2 ra1 ra0 ror gndo(rb) v cco(rb) rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 gndo(ga) v cco(ga) ga7 ga6 ga5 ga4 ga3 ga2 ga1 ga0 gor gndo(gb) v cco(gb) gb7 gb6 gb5 gb4 gb3 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vsync2 vsync1 coast ckext v ccd(slc) gndd(slc) acrx1 acrx2 csynco ckrefo cplo fieldo vsynco v cco(ttl) gndo(ttl) hpdo deo hsynco v ccd(mcf) gndd(mcf) stbydiv clp tck tdo dis scl sda a0 v ccd(i2c) gndd(i2c) gndo(clk) ckdata v cco(clk) gndo(ra) v cco(ra) ra7 gnda(b1) bin1 bin2 gnda(b2) bbot bclpc agco gndd(adc) v ccd(adc) gndd(sub) pwd test bb0 bb1 bb2 bb3 bb4 bb5 bb6 bb7 v cco(bb) gndo(bb) bor ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 v cco(ba) gndo(ba) gb0 gb1 gb2 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 tda8754hl v cco v cco v ccd v ccd v cco v ccd v ccd v ccd v ccd scl sda v cco v cco v cca v cca v cca sogin1 sogin2 rin1 gin1 gin2 rin2 v cca v cco v cco v cco v ccd bin1 bin2 c1 c4 1 m f c3 1 m f c6 330 pf c9 100 nf c10 100 nf c11 4.7 nf c14 100 nf c15 4.7 nf c7 1 m f c13 1 m f c16 1 m f c18 100 nf c17 1 m f c19 4.7 nf c12 1 m f c8 1 m f c5 330 pf c2 220 nf 680 pf r20 4.7 k w r21 4.7 k w out blue b out blue a out green b out green a out red b out red a fig.10 application diagram.
2004 may 18 51 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 15 package outlines unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.08 0.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
2004 may 18 52 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 1 a 1 b a 2 unit d y e references outline version european projection issue date 02-05-14 iec jedec jeita mm 1.65 0.45 0.35 1.20 0.95 17.2 16.8 y 1 17.2 16.8 e 1 e 2 15 15 0.55 0.45 0.12 0.35 dimensions (mm are the original dimensions) sot774-1 mo-192 - - - - - - e 0.25 v 0.1 w 0 5 10 mm scale sot774-1 lbga208: plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm a max. a a 2 a 1 detail x y y 1 c x d e c b a a b c d e f h k g j l m n p r t 246810121416 13579111315 ball a1 index area ball a1 index area e e e 1 b e 2 1/2 e 1/2 e a c c b ? v m ? w m
2004 may 18 53 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 16 soldering 16.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 16.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 may 18 54 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 16.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 may 18 55 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 17 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 18 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 may 18 56 philips semiconductors product speci?cation triple 8-bit video adc up to 270 msps tda8754 20 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r78/05/pp 57 date of release: 2004 may 18 document order number: 9397 750 13199

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